In the field of display technology, a thin film transistor is usually used as a switching element for controlling operations of a pixel unit. According to characteristics of silicon thin films in active layer of thin film transistor, thin film transistors can be classified into two types of amorphous silicon (a-Si) thin film transistors and polycrystalline silicon (poly-Si) thin film transistors. Amorphous silicon thin film transistors have defects such as low on-state current, low electronic mobility, poor stability, etc., and polycrystalline silicon thin film transistors have superior performances such as high electronic mobility, low leakage current, and so on. Therefore, a display apparatus with polycrystalline silicon thin film transistors has high resolution and fast speed of response. Further, low temperature poly-silicon (LTPS) thin film transistors have ability to integrate with peripheral circuits, and are superior to traditional amorphous silicon thin film transistors in terms of carrier mobility, threshold voltage and threshold swing.
As shown in FIG. 1 to FIG. 3, a shield metal (SM) 1, a buffer layer 2, an active layer 3, a gate insulator (GI) 4, a gate line 5, an inter-layer dielectric (ILD) 6, a data line (S/D) 7, a pixel electrode (PITO) 9, a passivation layer (PVX) 10, and a common electrode (CITO) 11 are successively provided on a substrate 14 of an existing array substrate comprising a LTPS thin film transistor, and the array substrate further comprises a planarization layer (not shown in the figure) provided between the data line 7 and the common electrode 11, wherein the data line 7 is connected with the active layer 3 through a first via hole 12, and the pixel electrode 9 is connected with the active layer 3 through a second via hole 13. The second via hole 13 further comprises a via hole in the planarization layer, or further comprises a via hole in the passivation layer. There are two overlapped regions between projections of the gate line 5 and the active layer 3 on the substrate 14, thus two active regions (also referred to channel regions while being conducting) are formed in the active layer 3. During manufacturing the above array substrate, in order to form patterns of the shield metal, the first via hole passing through the buffer layer, the active layer, the gate line, the second via hole passing through the gate insulator and the inter-layer dielectric, the data line, the via hole in the planarization layer, the pixel electrode, the via hole in the passivation layer, and the common electrode, ten patterning processes are often required.
The inventor of the present invention finds that, there are at least following problems in the prior art: with respect to the existing array substrate comprising a LTPS thin film transistor, the manufacturing process thereof is complex, the cost of production is high, and the distance between the layer of the data line and the layer of the pixel electrode is small and the edge of the pixel electrode overlaps with the data line, thus a large coupling capacitance is produced between the pixel electrode and the data line, resulting in a transmission delay of the signal on the data line, which influences the distribution of the liquid crystal molecules around the pixel electrode, in turn, can lead to poor displays on the display apparatus comprising the array substrate, for example, vertical moirés in lumps are generated in the pictures displayed on the display apparatus.